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Silicon Labs /SiM3_NRND /SIM3U167_B /TIMER_0 /CLKDIV

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Interpret as CLKDIV

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https://regviz.com/r/Silicon Labs/SiM3_NRND/SIM3L168_A/TIMER_1/CLKDIV#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKDIVRL0CLKDIVCT

Description

Module Clock Divider Control

Fields

CLKDIVRL

Clock Divider Reload Value.
CLKDIVCT

Clock Divider Counter.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data